/*
 * six_step.c
 *
 *  Created on: Feb 18, 2023
 *      Author: zes
 */

#include "six_step.h"

vu32 step = 1;

void six_step_init(void)
{
    GPIO_InitTypeDef GPIO_InitStructure={0};
    TIM_OCInitTypeDef TIM_OCInitStructure={0};
    TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure={0};
    TIM_BDTRInitTypeDef TIM_BDTRInitStructure={0};
    NVIC_InitTypeDef NVIC_InitStruct;

    RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOE | RCC_APB2Periph_TIM1, ENABLE );
    RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO,ENABLE);
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9|GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12|GPIO_Pin_13;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_Init( GPIOE, &GPIO_InitStructure );
    GPIO_PinRemapConfig(GPIO_FullRemap_TIM1,ENABLE);
    TIM_TimeBaseInitStructure.TIM_Period = 599;
    TIM_TimeBaseInitStructure.TIM_Prescaler = 95;
    TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
    TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_CenterAligned1;
    TIM_TimeBaseInit( TIM1, &TIM_TimeBaseInitStructure);
    TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
    TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
    TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
    TIM_OCInitStructure.TIM_Pulse = 299;
    TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
    TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
    TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
    TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset;

    TIM_OC1Init( TIM1, &TIM_OCInitStructure );
    TIM_OC2Init( TIM1, &TIM_OCInitStructure );
    TIM_OC3Init( TIM1, &TIM_OCInitStructure );
    TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Disable;
    TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Disable;
    TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
    TIM_BDTRInitStructure.TIM_DeadTime = 0x7F;
    TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
    TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
    TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
    TIM_BDTRConfig( TIM1, &TIM_BDTRInitStructure );
    TIM_CtrlPWMOutputs(TIM1, ENABLE );
    TIM_OC1PreloadConfig( TIM1, TIM_OCPreload_Enable );
    TIM_OC2PreloadConfig( TIM1, TIM_OCPreload_Enable );
    TIM_OC3PreloadConfig( TIM1, TIM_OCPreload_Enable );
    TIM_ARRPreloadConfig( TIM1, ENABLE );
    NVIC_InitStruct.NVIC_IRQChannel=TIM1_TRG_COM_IRQn;
    NVIC_InitStruct.NVIC_IRQChannelCmd=ENABLE;
    NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority=3;
    NVIC_InitStruct.NVIC_IRQChannelSubPriority=3;
    NVIC_Init(&NVIC_InitStruct);
    TIM_ITConfig(TIM1,TIM_IT_COM,ENABLE);
    TIM_Cmd( TIM1, ENABLE );
}

void TIM1_TRG_COM_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void TIM1_TRG_COM_IRQHandler(void)
{
    if(TIM_GetITStatus(TIM1, TIM_IT_COM))
    {
        TIM_ClearITPendingBit(TIM1,TIM_IT_COM);
        switch(step)
        {
            case 1:
            TIM_SelectOCxM(TIM1,TIM_Channel_1,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_1,TIM_CCx_Enable);
            TIM_CCxNCmd(TIM1,TIM_Channel_1,TIM_CCxN_Disable);

            TIM_CCxCmd(TIM1,TIM_Channel_2,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_2,TIM_CCxN_Disable);
            TIM_SelectOCxM(TIM1,TIM_Channel_3,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_3,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_3,TIM_CCxN_Enable);
            step++;
            break;

            case 2:
            TIM_CCxCmd(TIM1,TIM_Channel_1,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_1,TIM_CCxN_Disable);
            TIM_SelectOCxM(TIM1,TIM_Channel_2,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_2,TIM_CCx_Enable);
            TIM_CCxNCmd(TIM1,TIM_Channel_2,TIM_CCxN_Disable);
            TIM_SelectOCxM(TIM1,TIM_Channel_3,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_3,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_3,TIM_CCxN_Enable);
            step++;
            break;

            case 3:
            TIM_SelectOCxM(TIM1,TIM_Channel_1,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_1,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_1,TIM_CCxN_Enable);
            TIM_SelectOCxM(TIM1,TIM_Channel_2,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_2,TIM_CCx_Enable);
            TIM_CCxNCmd(TIM1,TIM_Channel_2,TIM_CCxN_Disable);
            TIM_CCxCmd(TIM1,TIM_Channel_3,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_3,TIM_CCxN_Disable);
            step++;
            break;

            case 4:
            TIM_SelectOCxM(TIM1,TIM_Channel_1,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_1,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_1,TIM_CCxN_Enable);
            TIM_CCxCmd(TIM1,TIM_Channel_2,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_2,TIM_CCxN_Disable);
            TIM_SelectOCxM(TIM1,TIM_Channel_3,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_3,TIM_CCx_Enable);
            TIM_CCxNCmd(TIM1,TIM_Channel_3,TIM_CCxN_Disable);
            step++;
            break;

            case 5:
            TIM_CCxCmd(TIM1,TIM_Channel_1,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_1,TIM_CCxN_Disable);
            TIM_SelectOCxM(TIM1,TIM_Channel_2,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_2,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_2,TIM_CCxN_Enable);
            TIM_SelectOCxM(TIM1,TIM_Channel_3,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_3,TIM_CCx_Enable);
            TIM_CCxNCmd(TIM1,TIM_Channel_3,TIM_CCxN_Disable);
            step++;
            break;

            case 6:
            TIM_SelectOCxM(TIM1,TIM_Channel_1,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_1,TIM_CCx_Enable);
            TIM_CCxNCmd(TIM1,TIM_Channel_1,TIM_CCxN_Disable);
            TIM_SelectOCxM(TIM1,TIM_Channel_2,TIM_OCMode_PWM1);
            TIM_CCxCmd(TIM1,TIM_Channel_2,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_2,TIM_CCxN_Enable);
            TIM_CCxCmd(TIM1,TIM_Channel_3,TIM_CCx_Disable);
            TIM_CCxNCmd(TIM1,TIM_Channel_3,TIM_CCxN_Disable);
            step=1;
            break;

            }
    }
}

void timer5_delay_1ms(void)
{
    TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure={0};
    NVIC_InitTypeDef  NVIC_InitStructure = {0};

    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE );

    TIM_TimeBaseInitStructure.TIM_Period = 5999;
    TIM_TimeBaseInitStructure.TIM_Prescaler = 95;
    TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
    TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
    TIM_TimeBaseInit( TIM5, &TIM_TimeBaseInitStructure);

    NVIC_InitStructure.NVIC_IRQChannel = TIM5_IRQn;
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
    NVIC_Init(&NVIC_InitStructure);

    TIM_ITConfig(TIM5,TIM_IT_Update,ENABLE);


    TIM_ARRPreloadConfig( TIM5, ENABLE );
    TIM_Cmd( TIM5, ENABLE );

}

void TIM5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void TIM5_IRQHandler(void)
{
    if(TIM_GetITStatus(TIM5,TIM_IT_Update))
    {
        TIM_ClearITPendingBit(TIM5,TIM_IT_Update);
        TIM_GenerateEvent(TIM1,TIM_EventSource_COM);
    }
}

void delay_1ms(void)
{
    Delay_Ms(1);
    TIM_GenerateEvent(TIM1,TIM_EventSource_COM);
}

